HD64570 Datasheet, PDF (253/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 5.23 Interrupts, Interrupt Sources, and Clearing Procedures (cont)
Interrupt
Interrupt Status Enable
Type
Bit
Bit
Interrupt Source
Source Enable
Status Bit Bit
Clearing
Procedure*¹
RXINT RXINT
interrupt
RXINTE (9)Overrun error
OVRN*² OVRNE 4
(10)CRC error
CRCE*² CRCEE
(11)End of message EOMF
(FST)
EOMFE
(12)Two-clock missing CLMD
detection
CLMDE
Clearing procedure 1: Write data to the transmit buffer until the data byte count in the buffer
becomes equal to or greater than TXF + 1, (TXF is the value specified with
TX ready control register 1 (TRC1)), or disable the transmitter.
Clearing procedure 2: Read data from the receive buffer until it becomes empty.
Clearing procedure 3: (1), (3) : Write a 1 to each status bit.
(2):Write data to the transmit buffer to place the transmitter in other state.
Clearing procedure 4: (1) − (12): Write a 1 to each status bit.
PMP: Read data from the receive buffer to enable reading the next
data*³.
CRCE: Automatically cleared when the CRC calculation result is
normal*⁴.
Notes: 1. The RXINT interrupt source can also be cleared by a channel reset or an RX reset
command. The TXRDY and TXINT interrupt sources can also be cleared by a channel
reset or a TX reset command.
2. Status register 2 (ST2) bit values are transferred to the frame status register (FST) and
ST2 is reset when the last character has been read from the receive buffer at
completion of receive frame transfer.
3. In CPU mode 1, the PMP bit is cleared when the parity/MP bit of the next data is 0,
(when the next data becomes ready to be read). In CPU modes 0, 2, and 3, this bit is
cleared when the parity/MP bit of the next two bytes of data are both 0 (when the next
two bytes of data become ready to be read).
4. CRC calculation result can be read from the CRCE bit when the CRCCC bit of mode
register 0 (MD0) is 1. For details on the setting/resetting timing of the CRCE bit, see
Error Checking, in section 5.3.2, Byte Synchronous Mode; and Error Checking, in
section 5.3.3, Bit Synchronous Mode.
Rev. 0, 07/98, page 237 of 453