HD64570 Datasheet, PDF (94/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CLK
BHE
A₀ to A₂₃
AS (ME)
WAIT
DMA read cycle
T₁
T₂
T₃
DMA write cycle
T₁
T₂
T₃
Memory address
Memory address
RD
WR
D₀ to D₁₅
(Out)
D₀ to D₁₅
(In)
Receive data
Transmit data
Data
latch point
No T_W states
CLK
DMA read cycle
T₁
T₂
T_W T₃
DMA write cycle
T₁
T₂
T_W
T₃
BHE
A₀ to A₂₃
Memory address
Memory address
AS (ME)
WAIT
RD
WR
D₀ to D₁₅
(Out)
D₀ to D₁₅
(In)
Receive data
Transmit data
Data
latch point
With T_W states
Figure 3.15 Master Mode Bus Timing Sequence in CPU Mode 0
Rev. 0, 07/98, page 78 of 453