HD64570 Datasheet, PDF (349/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Start
Read ST1 and ST2
(ACC ←ST1, ST2)
Clear interrupt
source bit
(ST2 ← ACC,
ST1 ←ACC)
Analyze interrupt source
Process interrupt
Issue EI instruction
Return
ACC: Accumulator
ST1: Status register 1
ST2: Status register 2
Figure 9.4 RXINT Interrupt Processing Routine (using HD64180)
9.1.4
Transmission in DMA Chained-Block Transfer Mode (Bit Synchronous HDLC
Mode)
Initialization: An example of an initialization program is given below.
CMD fl 21H........................................ Resets channel.
MD0 fl 87H........................................ Specifies bit synchronous HDLC mode.
Specifies CRC-CCITT mode, and presets to all 1s.
MD2 fl 00H........................................ Specifies the NRZ code.
Specifies full-duplex mode.
CTL fl 11H........................................ Specifies idle pattern transmission.
Specifies RTS line high-level output.
TRC0 fl 1FH........................................ TXRDY bit = 1 when the transmit buffer is not full.
TRC1 fl 1FH........................................ TXRDY bit = 0 when the transmit buffer is full.
Rev. 0, 07/98, page 333 of 453