HD64570 Datasheet, PDF (321/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

TCONRH
7
6
5
4
3
2
1
0
Read/Write
WWWWWWWW
Initial value
1
1
1
1
1
1
1
1
Timer constant 2¹⁵ 2¹⁴ 2¹³ 2¹² 2¹¹ 2¹⁰ 2 ⁹
2⁸
TCONRL
7
6
5
4
3
2
1
0
Read/Write
WWWWWWWW
Initial value
1
1
1
1
1
1
1
1
Timer constant 2⁷
2⁶
2⁵
2⁴
2³
2²
2¹
2⁰
Note: TCONR is a write-only register. It always reads 0000H.
7.2.3 Timer Control/Status Register (TCSR)
The timer control/status register (TCSR), provided for each of channels 0, 1, 2, and 3, requests
interrupts and controls the timer up-counter (TCNT) operation.
Bit name
Read/Write
Initial value
7
6
5
CMF ECMI —
R R/W —
0
0
0
4
3
TME —
R/W —
0
0
2
1
0
———
———
0
0
0
Compare match flag
Timer enable
0: TCNT and TCONR
are not equal
1: TCNT and TCONR
are equal
0: Stops incrementing
1: Starts incrementing
CMF interrupt enable
0: Disable
1: Enable
Note: Bit 5 and bits 3–0 are reserved.
These bits always read 0 and must be set to 0.
Rev. 0, 07/98, page 305 of 453