HD64570 Datasheet, PDF (27/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

1.6.3 MSCI Registers (1)
Address
CPU Modes 0 & 1
CPU Modes 2 & 3
Initial Value at Reset*¹
Read/
Write * ²
Register Name
Symbol Channel 0 Channel 1 Channel 0 Channel 1 MSB
LSB
Mode register 0
MD0 2EH
4EH
2FH
4FH
0 0 0 0 0 0 0 0 R/W
Mode register 1
MD1 2FH
4FH
2EM
4EH
0 0 0 0 0 0 0 0 R/W
Mode register 2
MD2 30H
50H
31H
51H
0 0 0 0 0 0 0 0 R/W
Control register
CTL 31H
51H
30H
50H
0 0 0 0 0 0 0 1 R/W
RX clock source register RXS 36H
56H
37H
57H
0 0 0 0 0 0 0 0 R/W
TX clock source register TXS 37H
57H
36H
56H
0 0 0 0 0 0 0 0 R/W
Time constant register TMC 35H
55H
34H
54H
0 0 0 0 0 0 0 1 R/W
Command register
CMD 2CH
4CH
2DH
4DH

W
Status register 0
ST0 22H
42H
23H
43H
00000000R
Status register 1
ST1 23H
43H
22H
42H
0 0 0 0 0 0 0 0 R/W
Status register 2
ST2 24H
44H
25H
45H
0 0 0 0 0 0 0 0 R/W
Status register 3
ST3 25H
45H
24H
44H
0 0 0 0 × ×*³ 0 0 R
Frame status register FST 26H
46H
27H
47H
0 0 0 0 0 0 0 0 R/W
Interrupt enable register 0 IE0
28H
48H
29H
49H
0 0 0 0 0 0 0 0 R/W
Interrupt enable register 1 IE1
29H
49H
28H
48H
0 0 0 0 0 0 0 0 R/W
Interrupt enable register 2 IE2
2AH
4AH
2BH
4BH
0 0 0 0 0 0 0 0 R/W
Frame interrupt enable FIE
2BH
4BH
2AH
4AH
0 0 0 0 0 0 0 0 R/W
register
Sync/address register 0 SA0 32H
52H
33H
53H
1 1 1 1 1 1 1 1 R/W
Sync/address register 1 SA1 33H
53H
32H
52H
1 1 1 1 1 1 1 1 R/W
Idle pattern register
IDL
34H
54H
35H
55H
1 1 1 1 1 1 1 1 R/W
Notes: 1. These initial values apply after a hardware reset or execution of a channel reset
command. Some registers are also initialized to these values by the RX reset command
or TX reset command. See section 5.2, Registers, for details.
2. The functions of some bits vary depending on the operating mode (asynchronous, byte
synchronous, or bit synchronous). See the register descriptions starting in section 5.2.1.
3. When bits 3 and 2 of status register 3 (ST3) are read, the logic level of the CTS and
DCD lines are read.
Rev. 0, 07/98, page 11 of 453