HD64570 Datasheet, PDF (234/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

ADPLL operating clock
(Operating mode: x 8)
Receive data
T_B
T_D
TC
T_B/4 T_B/2 T_B/4
Extracted clock
Receive data syncronized
with the extracted clock
T_S-2
T_S-1
T_S
T_S
T_B:
One receive data bit time
T_C:
One ADPLL operating clock cycle
T_D:
Delay time between the receive data input to the ADPLL and the receive data after
passing the noise suppressor and data delay unit
T_S-1 and T_S-2: Receive data level transitions after noise suppression
T_S:
Synchronized transitions of noise-suppressed receive data after noise suppression.
Figure 5.35 FM0 Receive Data Phase Compensation in Operating Mode × 8
The receive data noise suppression timing in the noise suppressor is shown in figure 5.36. NRZ
code receive data is used in this example. The same basic timing also applies to other codes.
The ADPLL samples receive data at the rising edge of the ADPLL operating clock pulse. In
operating mode × 8, the same receive data level sampled twice in succession is considered valid
data. (The same data level sampled three times in succession in operating mode × 16 and five
times in succession in operating mode × 32 is considered valid data.) All other sampled data is
suppressed as noise.
Å, Ç, and É in the figure correspond to "On", "Off", and "Undefined" in No. 4 of table 5.16,
ADPLL Specifications. É is suppressed as noise since the same level cannot be sampled twice in
succession.
Rev. 0, 07/98, page 218 of 453