HD64570 Datasheet, PDF (217/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Initialization by reset
RX
disable
state
"RX disable", "RX reset", or "Channel reset"
issued in any state
Flag detected (frame detected)
"RX enable"
issued
Flag detected
Data (other than
Flag
flag and abort)
detected
received
Flag wait state
Abort
Character
wait state
Address
OK
field check
state
detected
Flag detected
within 3-character
time (short frame)
1. Flag or abort not
detected
2. "Message reject"
not issued
Character
receive state
1. NG
2. Abort detected
Note:
1. Abort detected
2. "Message reject" issued
Command names are enclosed in double quotation marks (“ ”)
Figure 5.28 State Transition Diagram for Reception in Bit Synchronous Mode
Error Checking: Involves the following items.
• CRC errors
In bit synchronous HDLC mode, CRC-CCITT is usually used. Its initial value is all 1s, which
can be specified with the CRC1−CRC0 bits of MD0. (The CRC polynomial is X¹⁶ + X¹² + X⁵
+ 1 for CRC-CCITT.)
The transmitter and receiver both have a CRC calculator.
The CRC calculator is automatically initialized immediately before the A field transmission or
reception.
During transmission, CRC calculation is carried out on the data in the A, C, and I fields before
zero insertion.
Use the CRCCC bit of MD0 and the end of message command to enable CRC code
transmission. The CRC code is transmitted automatically when both the CRCCC bit and the
UDRNC bit of CTL are set to 1 in underrun state. For details, see section 5.2.1, MSCI Mode
Register 0 (MD0), section 5.2.4, MSCI Control Register (CTL), and section 5.2.8, MSCI
Command Register (CMD).
Rev. 0, 07/98, page 201 of 453