HD64570 Datasheet, PDF (150/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

TXRDY = 1: In TX enable state, indicates that the data byte count in the transmit buffer is
equal to or less than TXF0, or indicates that the data byte count in the transmit buffer is NOT
equal to or greater than TXF1 + 1 after the data byte count has temporarily been equal to or
less than TXF0.
The TXRDY bit has a hysteresis as shown in figure 5.2.
TXFIFO
32 bytes
TXF1 + 1
TXF0
0 byte
TXRDY = 1
TXRDY = 0
TXF1: A value set by the
TRC14 to TRC10 bits
TXF0: A value set by the
TRC04 to TRC00 bits
Figure 5.2 TXRDY Hysteresis
Writing a data word to the TX/RX buffer register (TRB) using the MPU with TXF1 set to 31
(1FH) eliminates the second byte of the data word. In this case, the TXRDY bit is asserted even
when 31 bytes of data are in the TX FIFO.
This situation does not occur in DMA transfer mode.
Bit 0 (RXRDY: RX Ready): Indicates the receive buffer status. This bit is set to 1 when the data
byte count in the receive buffer is equal to or greater than RXF + 1, (the value set by the RRC4−
RRC0 bits of the RX control register (RRC) + 1) regardless of the RX enable or RX disable status.
In bit synchronous mode, this bit is also set to 1 when data with EOM enters the receive buffer.
Once set to 1, this bit is not cleared until all the data has been read from the receive buffer.
An RXRDY interrupt request is issued to the MPU when this bit and the RXRDYE bit of IE0 are
both set to 1. A DMA request is issued to the on-chip DMAC when this bit is set to 1. For details,
see section 5.8.1, Serial Data Transfer by the MPU and DMAC.
• Asynchronous/Byte synchronous/Bit synchronous mode
RXRDY = 0: Indicates that the receive buffer is empty, or that, after the receive buffer is
empty, the data byte count in the receive buffer is NOT equal to or greater than RXF + 1. In
bit synchronous mode, this bit also indicates that no EOM data is in the receive buffer.
Rev. 0, 07/98, page 134 of 453