HD64570 Datasheet, PDF (202/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

A space detected where a stop bit should be causes a framing error. The FRME bit of ST2 is
set to 1 when the received data containing a framing error is ready to be read. Here, an
interrupt request is generated (if enabled). Even if the stop bit length is 1.5 or 2 bits, only the
first bit is checked.
For details on the FRME bit, see section 5.2.11, MSCI Status Register 2 (ST2).
A framing error does not stop the reception operation. In 1/1 clock mode, start bit searching
resumes at the clock cycle following detection of the framing error. In 1/16, 1/32, or 1/64
clock mode, searching resumes after a delay of a half-bit cycle that skips invalid stop bit(s).
Once the FRME bit is set to 1 by a framing error, it cannot be cleared even if subsequent data
causes no framing error. It can be cleared only when a 1 is written to the bit position or ST2 is
reset.
• Overrun error
An overrun error occurs when the receive buffer is full when new data is transferred.
When an overrun error occurs, the new data overwrites the bottom stage of the receive buffer,
erasing the previous data. At the same time, the bottom stage of the receive status FIFO is
overwritten with the status (indicating an overrun) of the new data.
The OVRN bit of ST2 is set to 1 when the overwritten data is ready to be read. Here, an
interrupt request is generated (if enabled). For details on the OVRN bit, see section 5.2.11,
MSCI Status Register 2 (ST2).
Even if an overrun error occurs, subsequent data is received normally. However, the OVRN
bit cannot be cleared even if the subsequent data causes no overrun error. It can be cleared
only when a 1 is written to the bit position or ST2 is reset.
Rev. 0, 07/98, page 186 of 453