HD64570 Datasheet, PDF (93/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Transfer of Three or More Bytes from Odd Address: In CPU modes 0, 2, and 3, to transfer
three or more bytes starting at an odd address by direct memory access, the DMAC first transfers
one byte from the odd address, then transfers successive words starting from the next even
address. If one byte remains to be transferred at the end, it is transferred from an even address.
Figure 3.14 shows an example of data transfer starting from an odd address.
D₁₅
D₈ D₇
D₀
D₁₅
D₈ D₇
D₀
2n + 7
—
(4) Byte transfer 2n + 6 2n + 6 (4) Byte transfer
—
2n + 7
2n + 5 ⁽³⁾
Word transfer
2n + 4 2n + 4 ⁽³⁾
Word transfer
2n + 5
2n + 3 ⁽²⁾
Word transfer
2n + 2 2n + 2 ⁽²⁾
Word transfer
2n + 3
2n + 1 ⁽¹⁾ Byte transfer
—
2n
2n
—
(1) _{Byte transfer 2n + 1}
(a) CPU Mode 0
(b) CPU Modes 2 and 3
2n, 2n + 1, ^… are addresses
Figure 3.14 Data Transfer from Odd Address (example)
Figures 3.15 to 3.17 show the master mode bus transfer timing sequence in each CPU mode.
Rev. 0, 07/98, page 77 of 453