HD64570 Datasheet, PDF (276/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

6.2.13 DMA Master Enable Register (DMER)
The DMA master enable register (DMER), shared by channels 0, 1, 2, and 3, enables or disables
DMA master operation. This register can be accessed only in byte units.
7
6
Single-block
transfer mode _{DME —}
Chained-block
transfer mode
Read/Write
Initial value
R/W —
1
0
5
4
3
2
1
0
———— ——
——————
0
0
0
0
0
0
DMA master enable
0: Disable
1: Enable
Note: Bits 6–0 are reserved. These bits always read 0 and must be set to 0.
Bit 7 (DME: DMA Master Enable): Enables or disables channels 0, 1, 2, or 3 in either single-
block transfer mode or chained-block transfer mode as follows.
DME = 0: Disables all channels
DME = 1: Enables channel(s) depending on the DE bit of the DMA status register (DSR) of each
channel
After reset, the value of the DME bit is 1.
Bits 6–0: Reserved. These bits always read 0 and must be set to 0.
Rev. 0, 07/98, page 260 of 453