HD64570 Datasheet, PDF (235/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

T_D
T_C
ADPLL operating clock
(operating mode: x 8)
Receive data
1
2
3
Noise-suppressed
2´
receive data
T_C: One ADPLL operating clock cycle
T_D: Delay time between the receive data input to the ADPLL and the receive data after passing the
noise suppressor and data delay unit
°: Receive data sampling points. The receive data is sampled at the rising edge of the ADPLL
clock pulse.
Figure 5.36 Noise Suppression in the Receive Data Noise Suppressor in Operating Mode × 8
Receive Clock Noise Suppression: The flow of receive data, the ADPLL operating clock signal,
and the receive clock signal for noise suppression are shown in figure 5.37.
Receive data
(For receive data)
Noise
suppressor
Data
delay unit
Noise-suppressed
receive data
ADPLL operating clock
(receive BRG output)
Receive clock
(RXC line input)
Multiplexor
Clock
extractor
Noise
suppressor
(For receive clock)
Noise-suppressed
receive data
Receive data
ADPLL operating clock
Receive clock
Figure 5.37 Data and Clock Signal Flow for Receive Clock Noise Suppression
The specific operations of the ADPLL are as follows:
• The receive data noise suppressor receives receive data and outputs the noise-suppressed
receive data.
• The ADPLL operating clock is supplied to the receive data noise suppressor and the receive
clock noise suppressor via the multiplexor.
• The receive clock noise suppressor outputs the noise-suppressed receive clock .
Rev. 0, 07/98, page 219 of 453