HD64570 Datasheet, PDF (274/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

6.2.12 DMA Priority Control Register (PCR)
The DMA priority control register (PCR), shared by channels 0, 1, 2, and 3, specifies channel
priority. When multiple channels request a DMA transfer, the channel given the highest priority
can use the bus. This register can be accessed only in byte units.
7
Single-block
transfer mode _—
Chained-block
transfer mode
6
5
4
3
2
1
0
— — BRC CCC PR2 PR1 PR0
Read/Write
Initial value
— — — R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
Bus release condition
Channel priority
0: No DMA request issued
1: One DMA transfer performed
by each channel
Channel change condition
0: Per bus cycle
1: No DMA request issued by
the corresponding channel
Note: Bits 7–5 are reserved. These bits always read 0 and must be set to 0.
Bits 7–5: Reserved. These bits always read 0 and must be set to 0.
Bit 4 (BRC: Bus Release Condition): Specifies the condition for the SCA to release the bus
control obtained in either single-block transfer mode or chained-block transfer mode as follows.
BRC = 0: The SCA releases the bus control when all DMA transfer requests have been processed.
BRC = 1: The SCA releases the bus control when every DMAC channel has performed one DMA
transfer according to the priority specified by the PR2–PR0 bits (channel priority bits)
of PCR. In this case, a channel releases the bus control when it has performed one
DMA transfer, and the bus control is given to a channel that has not performed a DMA
transfer. Bus control is switched between channels according to the CCC bit (channel
change condition bit ) of PCR. The SCA also releases the bus when all DMA transfer
requests have been processed, even when not all DMAC channels have performed one
DMA transfer.
Rev. 0, 07/98, page 258 of 453