HD64570 Datasheet, PDF (152/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.10 MSCI Status Register 1 (ST1)
Status register 1 (ST1) indicates status information such as break start/stop detection in
asynchronous mode, underrun error, and SYN pattern detection in byte synchronous mode,
underrun error, flag, abort, DPLL error, and idle start detection in bit synchronous mode, and also
indicates transmitter idle status, and CTS and DCD input level changes in all modes.
The reset descriptions of this register's bits are as follows:
• Bits 7, 4, 3, 2, 1, and 0 are reset when 1 is written to the corresponding bit.
• Bits 7, 6, and 3 are reset by a TX reset command.
• Bit 6 is reset when data is written to the transmit buffer.
• Bits 4, 2, 1, and 0 are reset by an RX reset command.
• All bits are reset by a channel reset command or in system stop mode.
When any bit of this register is set to 1, an MPU interrupt request is generated (if enabled).
Async
Byte sync
Bit sync
HDLC
Read/Write
Initial value
7
6
—*1 IDL
UDRN
5
4
3
2
1
0
—*2 —*1 CCTS CDCD BRKD BRKE
CLMD SYNCD
—*1 —*1
FLGD
ABTD IDLD
R/W R R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
Underrun error
DCD line
Break end
• Byte/Bit synchronous
mode
0: No underrun detected
1: Underrun detected
SYN pattern detection
• Byte synchronous mode
0: No pattern detected
1: Pattern detected
level change
0: Not changed
1: Changed
• Asynchronous mode
0: Break sequence end not detected
1: Break sequence end detected
Idle start detection
• Bit synchronous mode
Flag detection
0: Idle sequence start not detected
• Bit synchronous mode
1: Idle sequence start detected
0: No flag detected
1: Flag detected
CTS line
level change
Transmitter idle status
0: Not changed
0: Not idle
1: Changed
1: Idle
Two-clock missing detection
Break detection
• Asynchronous mode
0: Break sequence starts not detected
1: Break sequence starts detected
Abort detection
• Byte/Bit synchronous mode
• Bit synchronous mode
0: Two missing clock transitions not detected ^{0: Abort sequence start not detected}
1: Two missing clock transitions detected
1: Abort sequence start detected
Notes: ^{1. Reserved. These bits always read 0 and can be set to 0 or 1.}
2. Reserved. When read, this bit is undefined and must be set to 0.
Rev. 0, 07/98, page 136 of 453