HD64570 Datasheet, PDF (258/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

• Channels: 0, 2
B
H
L
23
16 15
87
0
Single-block transfer
mode
Chained-block
transfer mode
DARB
BARB
DARH
BARH
DARL
BARL
• Channels: 1, 3
B
H
L
23
16 15
87
0
Single-block transfer
mode
Chained-block
transfer mode
Not used
BARB
Not used
BARH
Not used
BARL
Figure 6.1 Destination Address Register/Buffer Address Register
6.2.2
Channels 0, 2: Chain Pointer Base (CPB)
Channels 1, 3: Source Address Register (SAR: SARL, SARH, SARB)/Chain
Pointer Base (CPB)
One set of three 8-bit subregisters, serving as the source address registers (SAR: SARL, SARH,
SARB) or chain pointer base (CPB) depending on the transfer mode, is provided for each of
channels 0, 1, 2, and 3 (figure 6.2).
Single-Block Transfer Mode: In single-block transfer mode, the three 8-bit sub-registers serve
as the source address registers (SAR: SARL, SARH, SARB) for specifying the 24-bit source
address of the data to be transferred. SARB, SARH, and SARL specify bits 23–16, 15–8, and 7–0
of the source address, respectively. This register can directly access a maximum of 16 Mbytes of
memory space.
This register must be set in DMA initial state.
After reset, the value of this register is undefined.
Rev. 0, 07/98, page 242 of 453