HD64570 Datasheet, PDF (284/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Register Setting: To start a memory-to/from-MSCI single-block transfer, follow the steps below
starting with the DMA in its initial state. (Steps 1 to 3 may be completed in any order.)
1. For memory-to-MSCI transfers, load the memory start address of the source into SAR. For
MSCI-to-memory transfers, load the memory start address of the destination into DAR.
2. Load the transfer byte count into BCR.
3. Clear the TMOD and CNTE bits of the DMA mode register (DMR) to specify single-block
transfer mode.
4. After steps 1 to 3, set the DE bit of the DMA status register (DSR) to 1 to start DMA operation.
External Bus Timing: The external bus timing in memory-to-MSCI single-block transfer mode
is shown in figure 6.11 and that in MSCI-to-memory single-block transfer mode is shown in figure
6.12. In the figures, wait states (T_W) are inserted between T₂ and T₃. In memory-to/from-MSCI
single-block transfer mode, one byte of data transfer (CPU mode 1) or one word of data transfer
(CPU modes 0, 2, and 3) is completed within one memory read or write cycle. Accordingly, high-
speed DMA transfer is possible.
Rev. 0, 07/98, page 268 of 453