HD64570 Datasheet, PDF (236/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Noise suppression timing in the receive clock noise suppressor is shown in figure 5.38. In this
example, operating mode × 8 is used. The same basic timing applies to other modes except for
the number of successive sampling times. The ADPLL samples the receive clock at the rising
edge of the ADPLL operating clock pulse. In operating mode × 8, the same receive data level
sampled twice in succession is considered valid data. (The same data level sampled three times in
succession in operating mode × 16 and five times in succession in operating mode × 32 is
considered valid data.) All other sampled data is suppressed as noise. If noise occurs around the
rising or falling edges of the receive clock pulses, the rising or falling edges of the noise-
suppressed receive clock pulses may be shifted forward or backward. The maximum shift widths
in × 8, × 16, and × 32 modes are 2, 3, and 5 ADPLL operating clock cycles, respectively.
Å and Ç in the figure correspond to "Off" and "On" in No. 5 of table 5.16, ADPLL Specifications.
Receive data noise is suppressed as described in Clock Component Extraction from Receive Data
above.
T _DC
ADPLL operating clock
(operating mode: x 8)
1
2
Receive data
Noise-suppressed
1´
receive data
T_DC: Delay time between the input receive clock and the receive clock after passing the noise
suppressor.
Figure 5.38 Noise Suppression in the Receive Clock Noise Suppressor
5.5.3 Notes on Usage
Synchronization patterns: By issuing an enter search command, FM-coded receive data can be
synchronized after only one transition. This command is effective in all operating modes
(× 8, × 16, or × 32).
When issuing an enter search mode command, for correct synchronization, use the following
synchronization patterns:
• FM0 11111111
• FM1 00000000
• Manchester 10101010 or 01010101
Rev. 0, 07/98, page 220 of 453