HD64570 Datasheet, PDF (288/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

HD64570
CPB (8 bits)
EDA (16 bits)
CDA (16 bits)
BAR (24 bits)
BCR (16 bits)
System memory
High-order 8 bits of the
descriptor address
Start address of the
read underflow descriptor
(low-order 16 bits)
Descriptor
Start address of the
descriptor being read
(low-order 16 bits)
Memory address of
the data being read
Byte count of the
data remaining in
the buffer being
transferred to the MSCI
Buffer
CPB: Chain pointer base
EDA: Error descriptor address register
CDA: Current descriptor address register
BAR: Buffer address register
BCR: Byte count register
: Empty buffer
: Data already transferred to MSCI
: Data to be transferred to MSCI
Figure 6.13 Memory-to-MSCI Chained-Block Transfer Mode
The operation flow in memory-to-MSCI chained-block transfer mode is shown in figure 6.13. As
shown in the figure, a DMA transfer starts with loading the contents of the descriptor specified by
CPB and CDA into the SCA internal registers. The DMAC then transfers data to the MSCI
transmitter from the buffer corresponding to the descriptor specified by CPB and CDA. At this
time, the DMAC writes the 24-bit memory address of the buffer currently being read to the buffer
address register (BAR) and the number of bytes remaining unread in the buffer to the byte count
register (BCR). When data transfer starts, the DMAC writes the BP value of the corresponding
descriptor to BAR and the data length (DL) value of the corresponding descriptor to BCR.
The BAR value is incremented by 1 or 2 each time one byte or one word of data is transferred,
respectively. Similarly, the BCR value is decremented by 1 or 2 each time one byte or one word
of data is transferred, respectively. When the BCR value reaches 0000H, the DMAC terminates
data transfer and updates the CDA value to indicate the start address of the next descriptor (buffer
switching), after which data is read from the buffer specified by the descriptor. In this way, the
DMAC transfers data from the buffers specified by the descriptor by updating the descriptors.
Rev. 0, 07/98, page 272 of 453