HD64570 Datasheet, PDF (278/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Buffer Pointer (BP) (24 Bits): Specifies the start address of the buffer corresponding to the
descriptor. The BP value is loaded into the buffer address register (BAR) at the start of transfer or
at buffer switching.
Data Length (DL) (16 Bits): Specifies the data length in the buffer corresponding to the
descriptor in byte units. The DL value is loaded into the byte count register (BCR) at the start of
transfer or at buffer switching.
This field is controlled by the MPU in memory-to-MSCI chained-block transfer mode.
Status (ST) (8 Bits): Indicates a frame transfer end or DMA transfer end for buffer data
corresponding to the descriptor.
This field is controlled by the MPU in memory-to-MSCI chained-block transfer mode.
ST configuration for memory-to-MSCI chained-block transfer mode (transmission) is shown in
table 6.1.
Table 6.1 Status Configuration (transmission)
Bit
Function
7
EOM
6
Not used
5
Not used
4
Not used
3
Not used
2
Not used
1
Not used
0
EOT
Note: Status bits 6–1 are not used in memory-to-MSCI chained-block transfer mode.
The functions of bit 7 and bit 0 are described below.
Bit 7 (EOM: End of Message): Indicates whether or not a frame transfer ends in the buffer
corresponding to the descriptor.
EOM = 0: Indicates that no frame ends in the buffer corresponding to the descriptor
EOM = 1: Indicates that a frame ends in the buffer corresponding to the descriptor
Bit 0 (EOT: End of Transfer): Specifies whether or not to terminate DMA transfer after the
current frame is transferred in multi-frame transfer mode.
EOT = 0: Does not terminate transfer
Rev. 0, 07/98, page 262 of 453