HD64570 Datasheet, PDF (305/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

The functions of the registers used in MSCI-to-memory chained-block transfer mode are shown in
table 6.7. As can be seen from the table, in MSCI-to-memory chained-block transfer mode, either
single-frame transfer or multi-frame transfer can be selected. In single-frame transfer mode,
transfer is completed within one frame, after which the DMAC enters initial state. Here, the DE
bit of DSR is automatically cleared. When the DE bit is set to 1 again, the DMAC restarts
operation. In multi-frame transfer mode, the DMAC subsequently transfers frames of data if a
request is issued from the MSCI. When the CDA and EDA values match, the DMAC terminates
data transfer, even if an additional transfer request has been issued.
Table 6.7 Control Registers Used in MSCI-to-Memory Chained-Block Transfer Mode
(reception)
Item
Chain Pointer Base
(CPB)
Error Descriptor
Address Register (EDA)
Current Descriptor
Address Register (CDA)
Number of 8
bits
16
16
Function
Specifies the high-order
Indicates the low-order
8 bits of the 24-bit descriptor 16 bits of the start address
start address.
of the descriptor following
the descriptor indicating the
last write-enabled buffer.
Specifies the low-order
16 bits of the start
address of the descriptor
corresponding to the first
receive buffer. This
address is updated by the
DMAC during buffer
chaining.
Role in —
—
When the DMAC begins
DMAC
receive operation,
operation
indicates the low-order
16 bits of the start
address of the descriptor
corresponding to the
buffer being written.
Transfer ends when a transfer request is issued while
the EDA and CDA match. An interrupt, if enabled, is
generated.
Register Under MPU control.
update
Under MPU control.
When the current buffer
write is completed, the
next descriptor start
address is automatically
loaded into this register.
Rev. 0, 07/98, page 289 of 453