HD64570 Datasheet, PDF (293/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 6.5 Memory-to-MSCI Chained-Block Single-Frame Transfer Mode (no transmit
data added during transmission)
DMAC
Step Operation
MPU
CDA EDA DE Bit
Operation Value Value Value Note
1
—
A₀ ‡ CDA A₀
A₃
1
A₃ ‡ EDA
1 ‡ DE bit
Specifies the first buffer containing
data to be transmitted using CDA,
and specifies the next to last buffer
using EDA. (see figure 6.15.)
2
Reads data —
from buffer 0
A₀
A₃
1
3
A₁ ‡ CDA
—
4
Reads data —
from buffer 1
A₁
A₃
1
A₁
A₃
1
5
A₂ ‡ CDA
—
0 ‡ DE bit
A₂
A₃
0
Clears the DE bit after the transfer
of one frame. When a 1 is written
to the DE bit, the DMAC can
accept a transfer request.
6
—
1 ‡ DE bit A₂
A₃
1
7
Reads data —
from buffer 2
A₂
A₃
1
8
A₃ ‡ CDA
—
0 ‡ DE bit
A₃
A₃
0
When a 1 is written to the DE bit,
and a transfer request is issued,
the DMAC generates a DMIA
interrupt. (see figure 6.15.)
A_n: Start address of each descriptor
CDA: Current descriptor address register
EDA: Error descriptor address register
DE bit: Bit 1 of the DMA status register (DSR)
Rev. 0, 07/98, page 277 of 453