HD64570 Datasheet, PDF (85/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CLK (CPU modes 1, 2, 3)
CLK (CPU mode 0)
BUSREQ
(CPU modes 1, 2, 3)
HOLD (CPU mode 0)
BUSACK
(CPU modes 1, 2, 3)
HOLDA (CPU mode 0)
BUSY
BEO
Input
Slave mode
DMA cycle
T_i
T₁ T₂ T₃
Output
Master mode
Example c
Figure 3.6 Bus Arbitration Sequence Examples (cont)
Input
Slave
mode
V_CC
BEO
SCA
BUSACK
BUSY
BUSREQ
Another
bus master
Bus arbiter
Higher MPU
Figure 3.7 Bus Arbitration System Block Diagram
Rev. 0, 07/98, page 69 of 453