HD64570 Datasheet, PDF (280/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

This field is controlled by the DMAC in MSCI-to-memory chained-block transfer mode. After
received data is loaded into the buffer, the DMAC loads the byte count of the data into this field.
Status (ST) (8 Bits): Indicates the status of the data in the buffer corresponding to the descriptor.
After data is loaded into the buffer, the DMAC loads the status of the data into this field.
This field is controlled by the DMAC in MSCI-to-memory chained-block transfer mode.
ST configuration for MSCI-to-memory chained-block transfer mode (reception) is shown in table
6.2.
Table 6.2 Status Configuration (reception)
Bit
Function
7
EOM
6
Short frame
5
Abort
4
Residual bit
3
Overrun
2
CRC
1
Not used
0
Not used
When a frame ends in the buffer corresponding to the descriptor, ST bit 7 to bit 0 are loaded with
the MSCI frame status register (FST) value, which is set immediately after the MSCI transmits the
end of frame from the receive buffer to the data bus. (For bit 7 to bit 0, see sections 5.2.11, MSCI
Status Register 2 (ST2), and 5.2.13, MSCI Frame Status Register (FST). When no frame ends in
the buffer corresponding to the descriptor and if the buffer is switched during one frame, ST bit 7
to bit 0 are cleared.
Rev. 0, 07/98, page 264 of 453