HD64570 Datasheet, PDF (201/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

8 bits/character D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
7 bits/character 0 D₆ D₅ D₄ D₃ D₂ D₁ D₀
6 bits/character 0 0 D₅ D₄ D₃ D₂ D₁ D₀
5 bits/character 0 0 0 D₄ D₃ D₂ D₁ D₀
Figure 5.20 Receive Character Format
Parity/MP Bit: An even or odd parity bit or an MP bit can be appended to transmit/receive
characters, as specified with the PMPM1−PMPM0 bits of MD1.
When an even parity bit is specified, the transmitter counts the number of 1s in the transmit
character and appends a 0 if the number is even or a 1 if the number is odd. In this way, the total
number of 1s actually transmitted should be even. The receiver checks whether or not the total
number of 1s in the received character and parity bit is even.
Similarly, when an odd parity bit is specified, the value of the parity bit is set so that the total
number of 1s transmitted should be odd.
When the MP bit is specified, an MP bit is appended to transmit and receive characters to enable
multiprocessor communication support.
For details, see Multiprocessor Support.
Error Checking: Involves the following items.
• Parity check
Received data is checked to see whether it has the proper parity.
When even parity is specified and the total number of 1s in the received character and the
parity bit is odd, the PE (parity error) bit of status register 2 (ST2) is set to 1 when the received
data containing the parity error is ready to be read. The situation for odd parity is the same
except that an even number of 1s triggers the error.
For details on the PE bit, see section 5.2.11, MSCI Status Register 2 (ST2).
Even if a parity error occurs, the data is received normally. However, the PE bit cannot be
cleared even if the subsequent data causes no parity error. It can be cleared only when a 1 is
written to the bit position or ST2 is reset.
When the PE bit is set to 1, an interrupt request is generated (if enabled).
• Framing error
Rev. 0, 07/98, page 185 of 453