HD64570 Datasheet, PDF (219/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

At message transmission completion, the MSCI enters closing flag transmit state when the
CRCCC bit of MD0 is 0, or enters FCS transmit state when the CRCCC bit is 1.
During reception, the MSCI assumes a flag detected in character receive state to be the end of
message.
When the CRCCC bit of MD0 is 1, characters up to and including the last character in the I field
are sent to the receive buffer, and FCS is deleted. The receive frame end status and CRC error
status associated with the last character are sent to the status FIFO and set to the EOM bit and
CRCE bit of ST2 when the last character becomes ready to be read. At the same time, the internal
DMAC is informed of the end of a frame, and an interrupt request is generated (if enabled).
When the CRCCC bit is 0, FCS is also sent to the receive buffer. In this case, its associated
receive frame end status is transferred to the status FIFO. To enable this control, characters are
sent to the receive buffer three character cycles after they are received. Thus, the last character in
the I field and the FCS have not yet been sent to the receive buffer when the MSCI detects a
closing flag.
Address Field Check: In bit synchronous mode, each data frame contains an address (A) field
which specifies what secondary station(s) should receive the frame. The MSCI supports four
address field check modes: address field no-check, single address 1, single address 2, and dual
address (table 5.13).
Table 5.13 Address Field Check
Mode
Address field no-check
Single address 1
Single address 2
Dual address
Function
Allows the MSCI to receive all frames
Allows the MSCI to receive only the frames whose A₁ field has the
specified value or global address (FFH)
Allows the MSCI to receive only the frames whose A₂ field has the
specified value or global address (FFH)
Allows the MSCI to receive only the frames whose A₁ and A₂ fields
have the specified values, global addresses (FFFFH), or group
addresses (A₂ = specified value, A₁ = FFH)
The ADDRS1−ADDRS0 bits of MD1 select an address field check mode, and synchronous/
address registers 0 and 1 (SA0 and SA1) specify the address. For details, see section 5.2.2, MSCI
Mode Register 1 (MD1), section 5.2.18, MSCI Synchronous/Address Register 0 (SA0), and
section 5 2.19, MSCI Synchronous/Address Register 1 (SA1).
Short Frame Detection: On detecting a short frame, the MSCI acts according to the frame
length, CRCCC bit value of MD0, and address field check mode as shown in table 5.14.
Rev. 0, 07/98, page 203 of 453