HD64570 Datasheet, PDF (29/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

1.6.5 DMA Registers Provided Separately for Channels 0 to 3
Address
CPU Modes 0 & 1
CPU Modes 2 & 3
Initial Value at
Hardware Reset
Read/
Write
Register
Name
Chan- Chan- Chan- Chan- Chan- Chan- Chan- Chan-
Symbol nel 0 nel 1 nel 2 nel 3 nel 0 nel 1 nel 2 nel 3
MSB
LSB
Destination DARL 80H A0H C0H E0H 81H A1H C1H E1H
address
(BARL)
register L
(buffer
address
register L)*¹
× × × × × × × × R/W
Destination DARH 81H A1H C1H E1H 80H A0H C0H E0H
address
(BARH)
register H
(buffer
address
register H)*¹
× × × × × × × × R/W
Destination DARB 82H A2H C2H E2H 83H A3H C3H E3H
address
(BARB)
register B
(buffer
address
register B)*¹
× × × × × × × × R/W
Source
SARL 
address
register L*²
A4H 
E4H 
A5H 
E5H × × × × × × × × R/W
Source
SARH 
address
register H*²
A5H 
E5H 
A4H 
E4H × × × × × × × × R/W
Source
SARB 86H A6H C6H E6H 87H A7H C7H E7H
address
(CPB)
register B
(chain pointer
base) * ¹
× × × × × × × × R/W
Current
descriptor
address
register L
CDAL 88H A8H C8H E8H 89H A9H C9H E9H
× × × × × × × × R/W
(×: undefined)
Notes: 1. Parentheses indicate registers with different functions in single-block transfer mode and
chained-block transfer mode. The name in parentheses applies in chained-block
transfer mode. See the register descriptions for details.
2. These registers are not used in chained-block transfer mode. Avoid writing to these
registers in chained-block transfer mode.
Rev. 0, 07/98, page 13 of 453