HD64570 Datasheet, PDF (246/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bit Rate
(bps)
f_CLK (MHz)
6
6.144
TMC BR CM Deviation (%) TMC BR CM Deviation (%)
38400 



5
0
1/32 0.00
19200 



5
0
1/64 0.00
9600 39
0
1/16 0.16
5
1
1/64 0.00
4800 39
0
1/32 0.16
5
2
1/64 0.00
2400 39
0
1/64 0.16
5
3
1/64 0.00
1200 39
1
1/64 0.16
5
4
1/64 0.00
600
39
2
1/64 0.16
5
5
1/64 0.00
300
39
3
1/64 0.16
5
6
1/64 0.00
150
39
4
1/64 0.16
5
7
1/64 0.00
110
213 2
1/64 0.03
109 3
1/64 0.08
TMC: Value of the TMC7−TMC0 bits of TMC
BR: Value of the TXBR3−TXBR0 bits of TXS or the RXBR3−RXBR0 bits of RXS
CM: Value of the BRATE1−BRATE0 bits of MD1 (clock mode in asynchronous mode (bit
rate/clock frequency))
Table 5.21 Register Set Values and Bit Rates in Asynchronous Mode (cont)
Bit Rate
(bps)
TMC BR
38400 13
0
19200 13
0
9600 13
0
4800 13
1
2400 13
2
1200 13
3
600
13
4
300
13
5
150
13
6
110
71
4
f_CLK (MHz)
8
CM Deviation (%) TMC BR
1/16 0.16
15
0
1/32 0.16
15
0
1/64 0.16
15
0
1/64 0.16
15
1
1/64 0.16
15
2
1/64 0.16
15
3
1/64 0.16
15
4
1/64 0.16
15
5
1/64 0.16
15
6
1/64 0.03
41
5
9.216
CM Deviation (%)
1/16 0.00
1/32 0.00
1/64 0.00
1/64 0.00
1/64 0.00
1/64 0.00
1/64 0.00
1/64 0.00
1/64 0.00
1/64 − 0.22
Rev. 0, 07/98, page 230 of 453