HD64570 Datasheet, PDF (30/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

1.6.5 DMA Registers Provided Separately for Channels 0 to 3 (cont)
Address
CPU Modes 0 & 1
CPU Modes 2 & 3
Initial Value at
Hardware Reset
Read/
Write
Register
Name
Chan- Chan- Chan- Chan- Chan- Chan- Chan- Chan-
Symbol nel 0 nel 1 nel 2 nel 3 nel 0 nel 1 nel 2 nel 3
MSB
LSB
Current
descriptor
address
register H
CDAH 89H A9H C9H E9H 88H A8H C8H E8H × × × × × × × × R/W
Error
descriptor
address
register L
EDAL 8AH AAH CAH EAH 8BH ABH CBH EBH × × × × × × × × R/W
Error
descriptor
address
register H
EDAH 8BH ABH CBH EBH 8AH AAH CAH EAH × × × × × × × × R/W
Receive
BFLL
buffer length
L*²
8CH 
CCH 
8DH 
CDH 
× × × × × × × × R/W
Receive
BFLH
buffer length
H* ²
8DH 
CDH 
8CH 
CCH 
× × × × × × × × R/W
Byte count BCRL 8EH AEH CEH EEH 8FH AFH CFH EFH × × × × × × × × R/W
register L
Byte count BCRH 8FH AFH CFH EFH 8EH AEH CEH EEH × × × × × × × × R/W
register H
DMA status DSR
register*¹
90H B0H D0H F0H 91H B1H D1H F1H 0 0 0 0 0 0 0 1 R/W
DMA mode DMR
register
91H B1H D1H F1H 90H B0H D0H F0H 0 0 0 0 0 0 0 0 R/W
End-of-frame FCT
interrupt
counter
93H B3H D3H F3H 92H B2H D2H F2H 0 0 0 0 0 0 0 0 R
DMA interrupt DIR
enable
register
94H B4H D4H F4H 95H B5H D5H F5H 0 0 0 0 0 0 0 0 R/W
DMA
DCR 95H B5H D5H F5H 94H B4H D4H F4H 
W
command
register
(×: undefined)
Notes: 1. Some bits in the DMA status register are cleared by writing 1 to their bit positions, and
one is a write-only bit. See section 6.2.7, DMA Status Register, for details.
2. These registers are used in receiving, so they are not provided for channels 1 and 3.
Rev. 0, 07/98, page 14 of 453