HD64570 Datasheet, PDF (232/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

established within a maximum of four transition points. (For FM type codes (FM0, FM1 and
Manchester), synchronization can be established in one level transition by issuing the enter search
mode command.)
The relationship between the extracted clock and the receive data bit cell depends on the receive
data code type. For NRZ and NRZI codes, the rising edge of the extracted clock pulse is located
at the midpoint of the data bit cell width that is output from the data delay unit. For FM0, FM1,
and Manchester codes, the rising edge of the extracted clock is located at the 1/4 point of the data
bit cell width that is output from the data delay unit. This applies also to operating modes × 16
and × 32 except that the maximum number of level transition points required for synchronization
is 8 and 16, respectively.
Phase compensation functions for NRZ codes and FM codes are summarizes in table 5.17.
Table 5.17 Phase Compensation for NRZ Codes and FM Codes
Codes
Receive Data Transition Points
NRZ
NRZI
Bit boundary to 1/2T_B
FM0
FM1
−1/2T_B to bit boundary
Bit boundary to 1/4T_B
−3/4T_B to bit boundary
Others
Manchester
1/2T_B to 3/4T_B
1/4T_B to 1/2T_B
Others
T_B: One bit cycle of receive data
Phase Compensation
−1 ADPLL operating clock
+1 ADPLL operating clock
−1 ADPLL operating clock (Note)
+1 ADPLL operating clock (Note)
No phase compensation
−1 ADPLL operating clock (Note)
+1 ADPLL operating clock (Note)
No phase compensation
1-bit width (T_B)
1
2
3
4
5
1, 5
2
3
4
: Bit boundaries
:
1
4
T_B
:
1
2
T_B
:
3
4
T_B
Note: An enter search mode command is automatically issued; the ADPLL automatically enters
search mode and attempts to reestablish synchronization at the next transition point if the
Rev. 0, 07/98, page 216 of 453