HD64570 Datasheet, PDF (413/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Address
Register
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
Wait Control
Wait Control Registers M
(WCRM)
05H
04H
Bit name
Read/Write
Initial value
7
6
5
4
3
2
1
0
—
— — — — PAMW2 PAMW1 PAMW0
— — — — — R/W R/W R/W
0
0
0
0
0
1
1
1
PAM area wait
Wait Control Registers H
(WCRH)
06H
07H
Bit name
Read/Write
Initial value
7
6
5
4
3
2
1
0
—
— — — — PAHW2 PAHW1 PAHW0
— — — — — R/W R/W R/W
0
0
0
0
0
1
1
1
PAH area wait
Not used
DMAC (General)
DMA Priority Control
Register (PCR)
07H 06H
08H
09H
7
Single-block
transfer mode _—
Chained-block
transfer mode
6
5
4
3
2
1
0
— — BRC CCC PR2 PR1 PR0
Read/Write
Initial value
— — — R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
Bus release condition
Channel priority
0: No DMA request issued
1: One DMA transfer performed
by each channel
Channel change condition
0: Per bus cycle
1: No DMA request issued by
the corresponding channel
Rev. 0, 07/98, page 397 of 453