HD64570 Datasheet, PDF (63/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 2.6 Bus Interface Lines (cont)
Pin Number
Symbol CP-84
WR/R/W 3
FP-88
14
A₀ /LDS 8
19
Input/
Output
Description
Input/
output
Master mode
Output line. When this line is
driven high, data moves in the
input direction. When this line
is driven low, data moves in
the output direction.
Slave mode
Input line. When this line is
driven high, data moves in the
output direction. When this line
is driven low, data moves in
the input direction.
Reset mode Input.
System stop Input.
mode
Input/ CPU modes 0, 1
output
Address: Least significant bit of the address
bus.
Master mode Output.
Slave mode Input.
Reset mode Input.
System stop Input.
mode
CPU modes 2, 3
Lower data strobe: Strobe timing for the low-
order data bits.
Master mode Output.
Slave mode Input.
Reset mode Input.
System stop Input.
mode
Rev. 0, 07/98, page 47 of 453