HD64570 Datasheet, PDF (273/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

The state transition diagram for three operating modes of the DMAC (initial state, enable state,
and halt state) is shown in figure 6.7.
Hardware reset
Mode
change
Address
write
Initial
state
Software abort
Software inhibit
DE ← 1
(Software)
Transfer
complete
Enable
state
DE ← 0
(Software)
DE ← 1
(Software)
Halt
state
Figure 6.7 Software Abort and DMAC Operation
When the DE bit of DSR is cleared by the MPU while the DMAC is enabled, the DMAC enters
halt state. Issuing a software abort command at this time causes the DMAC to enter initial state.
In this case, the DMA mode register (DMR), DSR, FCT, and DMA interrupt enable register (DIR)
retain their previous values. Note that software cannot cause the DMAC to enter initial state
directly from enable state.
Mode, address, and data length must not be changed during DMAC halt or enable state. If it is
necessary to change these values, the DMAC must be initialized by a software abort command in
advance. However, after a DMA transfer is completed (see table 6.3, DMAC Operating Modes, in
section 6.4.1, Overview), the DMAC is automatically placed in initial state, and no software abort
commands are necessary.
Rev. 0, 07/98, page 257 of 453