HD64570 Datasheet, PDF (38/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

1.7.6 Maximum Bit Rates
Table 1.2 lists the maximum bit rates supported by the MSCI in the SCA (when system clock
(fφ) = 10 MHz).
Table 1.2 Maximum Bit Rates
Maximum Transfer Rate (bps)
Clock Extraction
Sampling Clock:
External*¹
Sampling Clock:
BRG*^{2, 3}
Frequency Protocol
(fφ)
Mode
Clock External
Mode*⁴ Clock BRG
× 8 × 16 × 32 × 8 × 16 × 32
10 MHz*⁵ Asynchronous 1/64
62.5k*⁶ 78.1k*⁷   



1/32
125k*⁶ 156.3k*⁷   



1/16
250k*⁶ 312.5k*⁷   



1/1
4.0M*⁶ 3.3M*⁸   



Byte synchronous 1/1
7.1M*⁹ 5M*⁷
2.2M 1.1M 0.55M 1.25M 0.62M 0.31M
Bit synchronous 1/1
HDLC mode
7.1M*⁹ 5M*⁷
2.2M 1.1M 0.55M 1.25M 0.62M 0.31M
16.7 MHz*¹⁰ Asynchronous 1/64
104k*⁶ 130k*⁷   



1/32
208k*⁶ 260k*⁷   



1/16
416k*⁶ 521k*⁷   



1/1
6.67M*⁶ 5.56M*⁸   



Byte synchronous 1/1
12M*⁹ 8.3M*⁷ 2.2M 1.1M 0.55M 2.08M 1.04M 0.52M
Bit synchronous 1/1
HDLC mode
12M*⁹ 8.3M*⁷ 2.2M 1.1M 0.55M 2.08M 1.04M 0.52M
Notes: 1. 17.6 Mbps ÷ (sampling clock multiplier)
2. fφ ÷ (sampling clock multiplier)
3. Same maximum transfer rate when receive clock noise is suppressed
4. Depends on setting of MSCI mode register 1 (MD1)
5. SCA (HD64570CP, HD64570F)
6. fφ ÷ 2.5 × (clock mode)
7. fφ ÷ 2 × (clock mode)
8. fφ ÷ 3
9. fφ ÷ 1.4 × (clock mode)
10. High-speed SCA (HD64570CP16, HD64570F16)
Rev. 0, 07/98, page 22 of 453