HD64570 Datasheet, PDF (215/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Initialization by reset
No data remaining in transmit
buffer and "TX disable" not issued
"TX enable" issued
TX disable
state
Idle state
No data remaining
in transmit buffer
and "TX disable"
issued
No data remaining in
transmit buffer after
abort transmission
"TX reset" or
Data still in
"Abort transmission"
"channel reset"
transmit
issued several
issued in any state
buffer after
times
Transmit buffer
abort sent
Abort
empty after flag
transmit state
transmission
Data remaining
in transmit buffer
1. Underrun state
and UDRNC = 0
2. "Abort transmission"
issued
"Abort transmission"
issued
"Abort transmission"
issued
Opening flag
Character
FCS transmit
Closing flag
transmit state _After transmit state
state
After
transmit state
transmission
1. CRCCC = 1
transmission
and "EOM" issued
Data remaining in _{2. Underrun state,}
transmit buffer
CRCCC = 1, and UDRNC =1
and "EOM" not
issued
1. CRCCC = 0
and "EOM" issued
2. Underrun state,
CRCCC = 0, and UDRNC =1
Data remaining in transmit buffer after flag transmission
UDRNC: Underrun state control bit (control register (CTL) bit 5)
CRCCC: CRC calculation bit (mode register 0 (MD0) bit 2)
EOM: End of message command issued or completion of data transmission
signaled from the DMAC to MSCI during DMA chained-block transfer
Note: 1. Command names are enclosed in double quotation marks ("").
2. The state changes when character or pattern transmission is completed,
except when the transmitter is reset.
Figure 5.27 State Transition Diagram for Transmission in Bit Synchronous HDLC Mode
Reception Operation: Figure 5.28 is the state transition diagram for reception in bit synchronous
mode.
Rev. 0, 07/98, page 199 of 453