HD64570 Datasheet, PDF (379/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 10.25 MSCI Timing
(V_CC = 5 V ± 5%, V_SS = 0 V, Ta = 0 to +70°C unless otherwise specified)
Item
TXC cycle time (TXC input)
Symbol Min Typ
t _TCYC
1.4*¹ 
Max

Unit
t _CYC
TXC rise time (TXC input)
TXC fall time (TXC input)
TXC high-level pulse width
(TXC input)
t _TCr
t _TCf
t _TCHW




0.55 
10
ns
10
ns

t _CYC
TXC low-level pulse width
(TXC input)
t _TCLW
0.55 

t _CYC
TXD delay time (TXC input)
t _TDD1
30

90
ns
TXD delay time (TXC output)
t _TDD2


45
ns
RXC cycle time
t _RCYC
1.4*¹ 

t _CYC
RXC rise time
t _RCr


10
ns
RXC fall time
t _RCf


10
ns
RXC high-level pulse width
t _RCHW
0.55 

t _CYC
RXC low-level pulse width
t _RCLW
0.55 

t _CYC
RXD−RXC set-up time (RXC input) t_RDS1
15


ns
RXC−RXD hold time (RXC input) t_RDH1
10


ns
RXD−RXC set-up time (RXC output) t_RDS2
35


ns
RXC−RXD hold time (RXC output) t_RDH2
10


ns
ADPLL operating clock cycle time t_PLCY
57


ns
ADPLL operating clock rise time
t _PLr


8
ns
ADPLL operating clock fall time
t _PLf


8
ns
Timing
Figure 10.14
to figure 10.22
Rev. 0, 07/98, page 363 of 453