HD64570 Datasheet, PDF (268/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bit 3: Reserved. This bit always reads 0 and must be set to 0.
Bit 2 (NF: Number of DMA Frames): The function of this bit is described below.
• Single-block transfer mode
Reserved. When read, the value of this bit is undefined. This bit can be set to 0 or 1.
• Chained-block transfer mode
The NF bit specifies either single- or multi-frame chained-block transfer mode as follows.
This bit is reset to 0.
NF = 0: Specifies single-frame mode
NF = 1: Specifies multi-frame mode
Bit 1 (CNTE : Frame End Interrupt Counter Enable/Disable): The function of this bit is
described below.
• Single-block transfer mode
The CNTE bit must be set to 0.
• Chained-block transfer mode
The CNTE bit enables or disables the frame end interrupt counter (FCT) as follows. See
section 6.2.7, DMA Status Register (DSR), and section 6.2.9, Frame End Interrupt Counter
(FCT). This bit is reset to 0.
CNTE = 0: Disables FCT
CNTE = 1: Enables FCT
Bit 0: Reserved. This bit always reads 0 and must be set to 0.
6.2.9 Frame End Interrupt Counter (FCT)
The frame end interrupt counter (FCT), provided for each of channels 0, 1, 2, and 3, counts the
unprocessed interrupt requests which have occurred during multi-frame chained-block transfer.
This is a 4-bit read-only counter.
Rev. 0, 07/98, page 252 of 453