HD64570 Datasheet, PDF (466/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Address
Register
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
DMAC (Channel 3)
DMA Status Register
F0H
Channel 3: DSR Channel 3
F1H
7
6
5
4
3
2
Single-block
transfer mode
—— —
Chained-block ^EOT
——
transfer mode
EOM BOF COF
1
0
DE DWE
Read/Write
Initial value
R/W R/W R/W R/W —
0
0
0
0
0
— R/W W
0
0
1
DMA Mode Register
F1H
Channel 3: DMR Channel 3
F0H
End of transfer
0: Transfer not completed
1: Transfer completed
Counter overflow
• Chained-block
transfer
0: No error detected
1: Error detected
Buffer overflow/underflow
• Chained-block transfer
0: No error detected
1: Error detected
DMA enable
0: Disable
1: ^Enable
DE bit write enable
0: Enable
1: Disable
End of frame transfer
• Chained-block transfer
0: Frame transfer not completed
1: Frame transfer completed
7
6
5
4
3
2
1
0
Single-block
transfer mode _—
Chained-block
—
— TMOD —
—
CNTE —
transfer mode
NF
Read/Write
Initial value
— — — R/W — R/W R/W —
0
0
0
0
0
0
0
0
Not used
F2H F3H
DMA transfer mode
0: Single-block transfer
1: Chained-block transfer
Number of DMA frames
• Chained-block transfer
0: Single frame
1: Multi-frame
Frame end interrupt counter (FCT)
enable/disable
• Single-block transfer
Set this bit to 0
• Chained-block transfer
0: Frame end interrupt counter (FCT) disabled
1: Frame end interrupt counter (FCT) enabled
Rev. 0, 07/98, page 450 of 453