HD64570 Datasheet, PDF (95/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CLK
DMA read cycle
T₁
T₂
T₃
DMA write cycle
T₁
T₂
T₃
A₀ to A₂₃
AS (ME)
WAIT
Memory address
Memory address
RD
WR
D₀ to D₇
(Out)
D₀ to D₇
(In)
Receive data
Transmit data
Data
latch point
CLK
No T _W states
DMA read cycle
DMA write cycle
T₁
T₂
T_W T₃
T₁
T₂
T_W
T₃
A₀ to A₂₃
AS (ME)
WAIT
Memory address
Memory address
RD
WR
D₀ to D₇
(Out)
D₀ to D₇
(In)
Receive data
Transmit data
Data
latch point
With T_W states
Figure 3.16 Master Mode Bus Timing Sequence in CPU Mode 1
Rev. 0, 07/98, page 79 of 453