HD64570 Datasheet, PDF (266/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bit 4 (COF: Counter Overflow): The function of this bit is described below.
• Single-block transfer mode
Reserved. When read, the value of this bit is undefined. This bit can be set to 0 or 1.
• Chained-block transfer mode
The COF bit indicates an overflow in FCT; this bit is set to 1 when a frame transfer is
completed after the FCT value becomes 1111. At this time, the FCT value is reset to 0000.
This bit is cleared when a 1 is written to the bit position.
When this bit and the COFE bit of DIR are both 1, the DMAC generates an interrupt request
(DMIA). For details, see section 6.2.10, DMA Interrupt Enable Register (DIR).
Bits 3–2: Reserved. These bits always read 0 and must be set to 0.
Bit 1 (DE: DMA Enable): Enables or disables the corresponding DMA channel in either single-
block transfer mode or chained-block transfer mode as follows:
DE = 0: Disables the DMA channel 0, 1, 2, or 3
DE = 1: Enables the DMA channel 0, 1, 2, or 3
To write a value to the DE bit, a 0 must be written to the DWE bit at the same time. Transfer
starts when the request is issued while this bit is 1.
When the DMA transfer end condition is satisfied, the DE bit of the corresponding channel is
automatically cleared. For the DMA transfer end conditions, see section 6.4.1, Overview.
The DMAC enters halt state when a 0 is written to this bit during a transfer.
Bit 0 (DWE: DE Bit Write Enable): Enables write operation to the DMA enable (DE) bit in
either single-block transfer mode or chained-block transfer mode. To write a value to the DE bit,
a 0 must be written to the DWE bit at the same time. Since the value of this bit is not retained, a 0
must be written to the DWE bit each time any value is written to the DE bit.
When read, this bit always reads 1.
Rev. 0, 07/98, page 250 of 453