HD64570 Datasheet, PDF (187/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.25 MSCI Current Status Register 0 (CST0)
Current status register 0 (CST0) monitors the top stage of the MSCI's 32-stage status FIFO. This
register indicates whether or not data is in the top stage of the receive buffer, and if there is any
data, indicates the status of the data.
This register is reset under either of the following conditions:
• RX reset command
• Channel reset command
• System stop mode
No bit of this register generates any interrupt.
Async
Byte sync
7
6
5
4
3
2
1
— * PMPC0 PEC0 FRMEC0_OVRNC0 — ^* — ^*
—* —* —*
CRCEC0
Bit sync HDLC EOMC0SHRTC0ABTC0 RBITC0
Read/Write
R
R
R
R
R
R
—
Initial value
0
0
0
0
0
0
0
0
CDE0
R
0
Data status in the top stage of the receive buffer
Current data 0
0: No data exists
1: Data exists
Note: The bits marked with * are reserved. These bits always read 0.
Bits 7−2: Indicate the status of the data in the top stage of the receive buffer. These bits are
arranged in the same way as bits 7−2 of the status register (ST2). When data is in the top stage of
the receive buffer, the status of the top stage of the status FIFO is set to these bits. The status is
activated when the TX/RX buffer register (TRB) is ready to be read. When data is read from
TRB, the status of the data is cleared and replaced by the status of the following data. When there
is no subsequent data, the status remains cleared.
Bit 1: Reserved. This bit always reads 0 and must be set to 0.
Bit 0 (CDE0: Current Data 0): Indicates that data is in the top stage of the receive buffer. This
bit is set to 1 when TRB is ready to be read, and is cleared when data has been read and there is no
subsequent data.
CDE0 = 0: Indicates that no data is in the top stage of the receive buffer
Rev. 0, 07/98, page 171 of 453