HD64570 Datasheet, PDF (220/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 5.14 MSCI Actions at Short Frame Detection
Mode Settings
CRCCC Bit = 0
CRCCC Bit = 1
Frame Length Address Field
(excluding No-Check Single Single Address 2
flag)
Address 1
Dual Address
Address Field
No-Check Single Single Address 2
Address 1
Dual Address
Bits 1−8
Sends no data to Sends no data to the Sends no data to Sends no data to
the receive buffer. receive buffer.
the receive buffer. the receive buffer.
Bits 9−23
Sends a part of the Sends a part of the Sends no data to Sends no data to
data to the receive data to the receive the receive buffer. the receive buffer.
buffer.
buffer.
Appends the short Appends the short
frame status to the frame status to the last
last character and character and sets the
sets the SHRT bit SHRT bit of ST2.
of ST2.
Bits 24−31
Sends a part of the Sends a part of the Sends a part of Sends a part of
data to the receive data to the receive the data to the the data to the
buffer.
buffer.
receive buffer. receive buffer.
Appends the short Appends the short Appends the short Appends the short
frame status to the frame status to the last frame status to frame status to the
last character and character and sets the the last character last character and
sets the SHRT bit SHRT bit of ST2.
and sets the
sets the SHRT bit
of ST2.
SHRT bit of ST2. of ST2.
Bits 32−39
Receives the data
as normal data.
Sends a part of the Receives the data Sends a part of
data to the receive as normal data. the data to the
buffer.
receive buffer.
Appends the short
Appends the short
frame status to the last
frame status to the
character and sets the
last character and
SHRT bit of ST2.
sets the SHRT bit
of ST2.
Bits 40 or more Receives the data Receives the data as Receives the data Receives the data
as normal data. normal data.
as normal data. as normal data.
Note:
On detecting a short frame, the MSCI sets the SHRT bit of ST2 to 1. This automatically
sets the EOM bit to 1, indicating the end of a receive frame. At this time, an interrupt
request is generated (if enabled). Even if the MSCI detects a short frame, it does not set
the SHRT bit to 1, if data is not transferred to the receive buffer.
Rev. 0, 07/98, page 204 of 453