HD64570 Datasheet, PDF (380/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 10.25 MSCI Timing (cont)
Item
Symbol Min Typ Max Unit Timing
ADPLL operating clock high-level t_PLHW
10


ns
Figure 10.14
pulse width
to figure 10.22
ADPLL operating clock low-level t_PLLW
pulse width
10


ns
CLK−BRG output delay time*²
t _BGD


90
ns
TXC/RXC output rise time
t _BGr


30
ns
TXC/RXC output fall time
t _BGf


30
ns
RXC−SYNC set-up time
t _SYSU
2.5 

t _CYC
RXC−SYNC hold time
t _SYHD
2.5 

t _CYC
CTS high-level pulse width
t _CTSHW
2.0


t _CYC
CTS low-level pulse width
t _CTSLW
2.0 

t _CYC
DCD high-level pulse width
t _DCDHW
2.0


t _CYC
DCD low-level pulse width
t _DCDLW
2.0


t _CYC
CLK−RTS delay time
t _RTSD


70
ns
Notes: 1. In asynchronous mode and loop mode, t_TCYC and t_RCYC = 2.5 t_CYC (min).
2. f_BRG ≠ f_CLK (f_BRG is the baud rate generator output frequency; f_CLK is the system clock
(CLK) frequency.)
Table 10.26 Rise and Fall Times of Input Signals with No Characteristics Specified
(V_CC = 5 V ± 5%, V_SS = 0 V, Ta = 0 to +70°C unless otherwise specified)
Item
Input signal rise time
Input signal fall time
Symbol Min Typ Max Unit Timing
t _Ir


50
ns
Figure 10.23
t _If


50
ns
Rev. 0, 07/98, page 364 of 453