HD64570 Datasheet, PDF (106/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

4.2.6 Interrupt Status Register 2 (ISR2)
The read-only interrupt status register 2 indicates the status of interrupt request sources. Bits 7 to 4
are cleared to 0 at a reset. Bits 3 to 0 are reserved bits that always read 0.
7
6
5
4
3
2
1
0
Bit name T3IRQ T2IRQ T1IRQ T0IRQ — —
——
Read/Write
Initial value
R
R
R
R
————
0
0
0
0
0
0
0
0
Timer channel 3
interrupt request
0: Not requested
1: Requested
Timer channel 2
interrupt request
0: Not requested
1: Requested
Timer channel 0
interrupt request
0: Not requested
1: Requested
Timer channel 1
interrupt request
0: Not requested
1: Requested
Note: Initial values are the values after a hardware reset.
Rev. 0, 07/98, page 90 of 453