HD64570 Datasheet, PDF (290/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Start
CDA = EDA? ^Yes
No
Load chain pointer
(CP) (16 bits) into
DMAC work register
Load buffer pointer
(BP) (24 bits) into
BAR
Load data length
(DL) (16 bits) into
BCR
Load status (ST)
(8 bits) into DMAC
work register
Transfer one byte or one
word, decrement BCR,
and increment BAR
No
BCR = 0?
Yes
Load the next descriptor
start address from work
register to CDA
CDA:
EDA:
BAR:
BCR:
DE bit:
Current descriptor address
register
Error descriptor address
register
Buffer address register
Byte count register
DMA status register (DSR) bit 1
No
Transfer
completed?
Yes
End
(DE bit = 0)
Figure 6.14 Operation Flow in Memory-to-MSCI Chained-Block Transfer Mode
The functions of the registers used in memory-to-MSCI chained-block transfer mode are listed in
table 6.4. As can be seen from the table, in memory-to-MSCI chained-block transfer mode, either
a single-frame transfer or multi-frame transfer can be selected. In single-frame transfer mode,
Rev. 0, 07/98, page 274 of 453