HD64570 Datasheet, PDF (192/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Transmission Operation: Figure 5.13 is the state transition diagram for transmission in
asynchronous mode.
• TX disable state
The transmitter is placed in TX disable state by a hardware reset, a channel reset, a TX reset,
or a TX disable command. In this state, the TXD line is high (mark), and the TXRDY bit of
status register 0 (ST0) is cleared.
Data must not be written in the transmit buffer during the transmit disable state. At other times,
when writing data in the transmit buffer, the CPU should poll the TXRDY bit. Alternatively,
an interrupt or DMA transfer can be used.
• Idle state
The TX enable command sets the transmitter in idle state from TX disable state. In idle state,
the TXD line remains high (mark) until transmit data is written to the transmit buffer. When
the transmit data is written, the transmitter enters start bit transmit state.
• Start bit transmit state
The TXD line is low (space) for one bit cycle. Then the transmitter enters character transmit
state.
• Character transmit state
The transmitter transmits a character from the transmit buffer, beginning with the LSB.
• Parity/MP bit transmit state
The transmitter sends a parity or an MP bit as specified with the PMPM1−PMPM0 bits of
MD1. For details, see Parity/MP Bit below.
• Stop bit transmit state
The transmitter sends stop bit(s) as specified with the STOP1−STOP0 bits of MD0, and then
returns to idle state.
• Break transmit state
The TXD line goes low (space). The transmitter transmits a break when the BRK bit of the
control register (CTL) is set to 1. The TXD line remains low until the BRK bit is cleared.
• One-bit cycle mark transmit state
The TXD line goes high (mark) and remains so for one bit cycle after the break transmit state
is canceled.
Rev. 0, 07/98, page 176 of 453