HD64570 Datasheet, PDF (367/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 10.12 MSCI Timing
(V_CC = 5 V ± 10%, V_SS = 0 V, Ta = −20 to +75°C unless otherwise specified)
Item
TXC cycle time (TXC input)
Symbol Min Typ
t _TCYC
1.4*¹ 
Max
 *³
Unit
t _CYC
TXC rise time (TXC input)
TXC fall time (TXC input)
TXC high-level pulse width
(TXC input)
t _TCr
t _TCf
t _TCHW
TXC low-level pulse width
(TXC input)
t _TCLW
TXD delay time (TXC input)
t _TDD1
TXD delay time (TXC output)
t _TDD2
RXC cycle time
t _RCYC
RXC rise time
t _RCr
RXC fall time
t _RCf
RXC high-level pulse width
t _RCHW
RXC low-level pulse width
t _RCLW
RXD−RXC set-up time (RXC input) t_RDS1
RXC−RXD hold time (RXC input) t_RDH1
RXD−RXC set-up time (RXC output) t_RDS2
RXC−RXD hold time (RXC output) t_RDH2
ADPLL operating clock cycle time t_PLCY
ADPLL operating clock rise time
t _PLr
ADPLL operating clock fall time
t _PLf




0.55 
0.55 




1.4*¹ 




0.55 
0.55 
30

20

80

20

57





10
ns
10
ns

t _CYC

t _CYC
95
ns
50
ns
 *³
t _CYC
10
ns
10
ns

t _CYC

t _CYC

ns

ns

ns

ns

ns
8
ns
8
ns
Timing
Figure 10.14
to figure 10.22
Rev. 0, 07/98, page 351 of 453