HD64570 Datasheet, PDF (24/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Internal address bus/data bus
Physical address boundary
register 0 (PABR0)
Physical address boundary
register 1 (PABR1)
Wait control unit
Wait control register L
(WCRL)
Wait control register M
(WCRM)
Wait control register H
(WCRH)
WAIT line
Wait control signal
Figure 1.5 Wait Controller Block Diagram
1.5 Protocol Support
1.5.1 Asynchronous Mode
Item
Character length
Parity
Stop bits
Transmit/receive clock
Error detection
Break signal
Break detection
Multiprocessor support
Description
5 to 8 bits
Odd or even parity or no parity
1, 1.5, or 2
1x, 16x, 32x, or 64x mode
Parity errors, overrun errors, framing errors
Can generate break signal of arbitrary length
Detects beginning and end of break
By MP bit
Rev. 0, 07/98, page 8 of 453