HD64570 Datasheet, PDF (14/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.7.3 Interrupt Enable Conditions ................................................................................. 237
5.8 Reset Operation ................................................................................................................. 237
Section 6 Direct Memory Access Controller (DMAC).......................................... 239
6.1 Overview............................................................................................................................ 239
6.1.1 Functions .............................................................................................................. 239
6.1.2 Configuration and Operation................................................................................ 240
6.2 Registers ............................................................................................................................ 241
6.2.1 Channels 0, 2: Destination Address Register (DAR: DARL, DARH, DARB)/
Buffer Address Register (BAR: BARL, BARH, BARB)
Channels 1, 3: Buffer Address Register (BAR: BARL, BARH, BARB) .......... 241
6.2.2 Channels 0, 2: Chain Pointer Base (CPB)
Channels 1, 3: Source Address Register (SAR: SARL, SARH, SARB)/
Chain Pointer Base (CPB).................................................................................... 242
6.2.3 Current Descriptor Address Register (CDA: CDAL, CDAH) ............................ 244
6.2.4 Error Descriptor Address Register (EDA: EDAL, EDAH) ................................ 245
6.2.5 Receive Buffer Length Register (BFL: BFLL, BFLH) ....................................... 246
6.2.6 Byte Count Register (BCR: BCRL, BCRH) ....................................................... 247
6.2.7 DMA Status Register (DSR) ................................................................................ 248
6.2.8 DMA Mode Register (DMR) ............................................................................... 251
6.2.9 Frame End Interrupt Counter (FCT) .................................................................... 253
6.2.10 DMA Interrupt Enable Register (DIR)................................................................. 254
6.2.11 DMA Command Register (DCR)......................................................................... 256
6.2.12 DMA Priority Control Register (PCR)................................................................. 258
6.2.13 DMA Master Enable Register (DMER) ............................................................... 260
6.3 Descriptors......................................................................................................................... 261
6.3.1 Memory-to-MSCI Chained-Block Transfer Mode (Transmission) ..................... 261
6.3.2 MSCI-to-Memory Chained-Block Transfer Mode (Reception)........................... 263
6.4 Operating Modes ............................................................................................................... 265
6.4.1 Overview .............................................................................................................. 265
6.4.2 Memory-to/from-MSCI Single-Block Transfer Mode......................................... 267
6.4.3 Memory-to-MSCI Chained-Block Transfer Mode .............................................. 271
6.4.4 MSCI-to-Memory Chained-Block Transfer Mode .............................................. 285
6.4.5 DMAC Characteristics ......................................................................................... 299
6.5 Interrupts............................................................................................................................ 300
6.6 Reset Operation ................................................................................................................. 301
6.7 Precautions ........................................................................................................................ 301
Section 7 Timer .................................................................................................................. 303
7.1 Overview............................................................................................................................ 303
7.1.1 Functions .............................................................................................................. 303
7.1.2 Configuration and Operation................................................................................ 303
7.2 Registers ............................................................................................................................ 304
Rev. 0, 07/98, page iv of 11