HD64570 Datasheet, PDF (263/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

This register must be set in DMA initial state. In single-block transfer mode, the byte counter
register (BCR) must not be 1 in CPU modes 0, 2, and 3, since data may be transferred in word
units. To transmit/receive only one byte of data, data must be directly written to or read from the
MSCI TX/RX buffer register (TRB), instead of using the on-chip DMAC.
The above restrictions do not apply to CPU mode 1.
After reset, the value of this register is undefined.
Chained-Block Transfer Mode: In this mode, BCR indicates the number of bytes remaining in
the buffer currently being accessed. When the BCR value becomes 0000H, read/write access to
the current buffer terminates, and the next buffer becomes available. At this time, the BCR value
is updated, either to the byte length stored in the descriptor data length for a memory-to-MSCI
transfer (transmission: buffer read), or to the value of the receive buffer length register (BFL) for
an MSCI-to-memory transfer (reception: buffer write).
The MPU cannot write to this register in this mode.
After reset, the value of this register is undefined.
H
L
15
87
0
Single-block transfer
mode
Chained-block
transfer mode
BCRH
BCRL
Figure 6.6 Byte Count Register
6.2.7 DMA Status Register (DSR)
The DMA status register (DSR), provided for each of channels 0, 1, 2, and 3, indicates the status
of a DMA transfer. This register also enables or disables each DMAC channel.
Rev. 0, 07/98, page 247 of 453