HD64570 Datasheet, PDF (384/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 10.30 CPU Mode 1 Slave Mode Bus Timing
(V_CC = 5 V ± 10%, V_SS = 0 V, Ta = −40 to +85°C unless otherwise specified)
Item
Symbol Min Typ Max Unit Timing
Address set-up time
t _ADS
30


ns
Address hold time
t _ADH
0


ns
CS set-up time
t _CSS
30


ns
CS hold time
t _CSH
0


ns
RD active set-up time
t _RDS1
30


ns
RD inactive set-up time
t _RDS2
30


ns
RD inactive hold time
t _RDH1
10


ns
RD active hold time
t _RDH2
0


ns
WR active set-up time
t _WRS1
30


ns
WR inactive set-up time
t _WRS2
30


ns
WR inactive hold time
t _WRH1
10


ns
WR active hold time
t _WRH2
0


ns
WAIT active delay time
t _WTD1


50
ns
WAIT inactive delay time
t _WTD2


60
ns
Read data active delay time
t _DBD1


60
ns
Read data hold time
t _DBD2
6


ns
Read data floating delay time
t _DBZ


60
ns
Write data set-up time
t _DBS
25


ns
Write data hold time
t _DBH
20


ns
Note: The CLK timing is the same in this mode and DMA mode. See table 10.8.
Figure 10.2
Rev. 0, 07/98, page 368 of 453